Comparison of Conventional low Power Flip Flops with Pulse Triggered Generation using Signal Feed through technique
نویسندگان
چکیده
Abstract— the objective to design and compare a low-power flip-flop (FF) design presenting an explicit type pulsetriggered framework. Pulse triggered method use used for clock to resolves lengthy discharging path issue in conventional explicit type pulse-triggered FF (P-FF) design and achieves better rate and energy efficiency. A novel power effective pulse triggered flip-flop design with lowest no. of transistors is suggested. Various publish structure simulator outcomes based on Mentor Eldo Simulator CMOS 180-nm technology.
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